1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which includes a circuit for separately generating a bit line equalize signal and bit line precharge signal and separately supplying them to the corresponding bit lines for a memory cell and a circuit for preventing an entry of write data from being made, for a predetermined period of time, by a resetting operation and ensures an adequate operation margin against a data hold time.
2. Description of the Prior Art
In a conventional semiconductor memory device, a precharge and equalize signals generating circuit is connected to memory cells to generate a precharge signal for precharging the corresponding memory cell and an equalize signal for equalizing the corresponding memory cell. In this semiconductor memory device, an ideal design is sought to achieve a write recovery time be equal to zero. In this state, the precharge/equalize signal is generated to hold the bit line potential at a high(Vcc-Vth) potential level.
However, in the conventional semiconductor memory device, even in the event of a transition to an address of the next cycle during the data write operation, a high potentials appear on the paired bit lines during the generation of a precharge and equalize signals, no write error occurs, but at the completion of the precharge/equalize signal, a write error will occur.
To solve the above problem, the conventional semiconductor memory device disclosed in U.S. Pat. No. 5,091,889 ensured a margin of a write recovery time by precharging data line pair during an address state transition pulse period generated by detecting the address state transition after a write operation, in addition to precharging the data line pair by a signal generating circuit during the write operation. Therefore, even though an invalid address is input, the conventional semiconductor memory device can not write data to memory cell during the period.